The present invention relates to multi-bit sigma-delta analog-to-digital converter and, more particularly, to a multi-bit sigma-delta analog-to-digital converter having an adaptively randomizable data weighted averaging algorithm dynamic element matching logic block.
Conversion of analog signals to digital signals and vice versa interfaces real world systems with digital systems that read, store, interpret, manipulate and otherwise process the discrete values of sampled analog signals, many of which vary. Real world applications that convert digital signals to analog waveforms at a high resolution include systems such as, digital audio systems such as compact disc players, digital video players, and various other high performance audio applications.
Sigma-delta modulators (SDMs) have come into widespread use as a processing solution regarding these real world digital audio applications to provide a high resolution data conversion solution using low resolution building blocks. A low resolution building block, such as the single-bit DAC, provides perfect linearity which the single-bit SDM relies upon to achieve high resolution. In addition, the single-bit SDM has low sensitivity to analog component matching and large over-sampling ratios (OSRs), making it the preferred architecture for the past decade. These large OSRs arise from the inherent linearity of the single-bit DAC and the extremely small input bandwidth. To obtain higher resolution or wider bandwidth, however, higher order loops are required. Higher order loops, however, cause instability problems, resulting in reduced input range.
Multi-bit, multi-stage SDMs (MASH) relax the instability problem and require lower oversampling ratios (OSRs). The MASH architecture can provide a signal to quantization noise ratio (SQNR) greater than 16 bits even with OSRs as low as 8. The first stage of a conventional MASH architecture, as shown in FIG. 1, includes an n-bit ADC and an n-bit DAC in its feedback path. Generally, the ADC and DAC within the MASH architecture include discrete data elements, such as, capacitors, resistors, current sources and the like for converting electrical signals from analog to digital form and vice versa. Particularly, the DAC includes a bank of capacitors configured such that a selected number of capacitors release their electrical energy into a summing junction that produces an analog output signal equivalent to the digital input. Conversely, the ADC includes comparators combined with a voltage divider network such that each comparator compares the same reference voltage to an incrementally higher voltage level associated with the incoming analog signal. A common clock triggers the output of the comparators, such that each comparator generates a high logic (1) or a low logic (0) level with the parallel output of the comparators representing a digital xe2x80x9cthermometer codexe2x80x9d indicative of the incoming analog voltage level. This thermometer code may then be digitally processed to generate an n-bit digital word representing the converted analog signal.
Since some degree of variation exists among identically modeled elements due to manufacturing variations, imperfections in materials used, change in temperature, humidity, degradation, etc., noise results. In particular, any mismatch in the unit elements of the DAC causes non-linearity in the feedback path, which manifests itself as distortion as well as noise at the output. Thus, the major disadvantage of the MASH architecture is that the multi-bit DAC in the feedback path does not possess the inherent linearity of the single-bit DAC and, thus, produces distortion in the signal path.
Though component mismatches down to 0.1% can be achieved with known technologies, this is not sufficient to achieve specifications above 100 dB spurious free dynamic range (SFDR). The problem is more severe for high speed modulators having low OSRs. FIGS. 2a and 2b illustrate the frequency spectrum at the output of a typical 2-1-1 multistage SDM having a 3-bit DAC in the first stage, where the input bandwidth is 2.5 MHz and the OSR is eight. FIG. 2a displays the modulator output where the unit elements have a mismatch of 0% and FIG. 2b displays the modulator output where the unit elements have a mismatch of 0.1%. As implied by FIG. 2b, even a small mismatch in the unit elements can increase the noise floor and the tones substantially, thereby reducing both the signal-to-noise ratio plus distortion (SNRD) and SFDR, substantially.
There are several approaches to correct the effects of unit element mismatch. The first approach incorporates trimming the unit elements to cancel the noise at the output. Trimming, however, is expensive and hence is not suited for a low cost semiconductor environment. Another approach incorporates calibration or error correction associated with all unit elements within the SDM. This second approach, however, is very complex to implement and attempts towards commercial use have not been successful to date. The last known approach implements shaping the spectrum of DAC mismatch through the use of dynamic element matching (DEM) algorithms which algorithmically manipulate the selection of the data converter unit elements to provide a noise shaping of the mismatch errors associated with these elements.
Various DEM algorithms have been proposed to date to either randomize or shape the errors caused by the unit elements within the multi-bit DAC. Known available DEM algorithms have significant disadvantages in terms of performance as well as complexity. The most widely used DEM algorithm, data-weighted averaging (DWA), provides a good attenuation of DAC noise by ideally achieving a first-order noise shaping. Assuming the 3-bit DAC is implemented using 8 unit element capacitors, the operation of the DWA algorithm can be explained using FIGS. 3a, 3b and 3c. As shown, an input sequence of 2, 4, and 6 provides the starting points of the selected unit elements: A, G and C; wherein, the starting point is incremented based upon the input sequence. This ensures maximum usage of each unit element in an effort to average out each individual error associated with each unit element and, thus, provide a first order shaping of the noise associated with the multi-bit DAC. In this manner, the unit elements of the data converter may equally participate in the conversion process, thereby minimizing the effects of mismatched elements in a data converter by distributing errors due to mismatched elements.
Since the pointer increment is dependent upon input data, the DWA algorithm is dependent upon the amplitude and frequency of the input signal. As such, the conventional DWA algorithm produces in-band tones for smaller input amplitudes, which reduces the SFDR drastically as is shown by comparison of the in-band spectrum representations of the SDM output as shown in FIGS. 4a and 4b, wherein the input signals are xe2x88x924 dB and xe2x88x9225 dB, respectively. As shown, the amplitude and location of the in-band tones depends upon the input signal amplitude. Some of the tones appear as harmonics, thereby, reducing total harmonic distortion (THD) as well.
Furthermore, the DWA algorithm can cause folding of DAC out-of-band tones into the baseband which results in the reduction of SDM performance, reducing the SFDR drastically, particularly in modulators having a reduced over-sampling ratio. These tones, depending upon the input signal amplitude, move around within the input bandwidth. Many versions of DWA have been proposed in an attempt to eliminate these in-band tones resulting from the DWA algorithm. In a first approach, DWA aliasing tones in a multi-bit SDM can be broken up and randomized by adding dither, at the cost of increasing baseband noise, reducing dynamic range, and possibly destabilizing the modulator.
U.S. Pat. No. 6,218,977, incorporated herein by reference, discloses a method and apparatus for distributing mismatched error associated with data converter elements using a rotator circuit. The rotator circuit includes a barrel shifter coupled to receive the digital output to shift the output by an amount determined by an encoder pointed to a table look-up value which supplies the appropriate clocked delay to the barrel shifter. This output is fed back into the DAC for conversion and summation with the input signal to cancel the effects of the error in the unit elements of the DAC. This approach, however, implements the conventional DWA algorithm which produces in-band tones for smaller input amplitudes, and, thus, substantially reduces the SFDR.
Other approaches include: rotated DWA, extra unit element DWA, Offset DWA, randomized DWA (RnDWA), Bi-DWA, and partitioned DWA. All of these solutions, however, either increase complexity or reduce signal to noise ratio plus distortion (SNRD) or both.
Specifically, the RnDWA as disclosed in xe2x80x9cTechniques for Preventing Tonal Behavior of Data Weighted Averaging Algorithm in Sigma-Delta Modulators,xe2x80x9d Morteza Vadipour, IEEE Transactions On Circuits and Systemsxe2x80x94II: Analog and Digital Signal Processing, Vol. 47, No. 11, November 2000, (which is incorporated by reference herein) is implemented in such a way that no unit is reselected before all the other units are reselected. Each selection is random in nature and is dependent upon every element being selected once prior to reselection of an element. This ensures that the sum of errors remains small and random, assuming that the DAC is offset free and gain is ideal. Although the RnDWA implementation as disclosed in the Vadipour paper improves the SFDR of a signal, the SNRD will decrease which is not desirable. The RnDWA is also complex to implement; and, thus, is not a cost effective solution.
Thus, a need exists for a multi-bit SDM incorporating a dynamic element matching algorithm that gives a first order noise shaping of errors associated with the unit elements of the multi-bit DAC, without creating large in-band tones. This multi-bit SDM must drastically reduce in-band tones associated with DWA while maintaining SNRD at high input signal amplitudes.
To address the above-discussed deficiencies of multi-bit sigma-delta modulators (SDM), the present invention teaches an SDM which gives a first order noise shaping of the errors associated with the multi bit DAC employing unit elements, without creating large in-band tones. The SDM includes a summer connected to an analog loop filter having an inverse noise shaping function which processes the analog input signal. A multi-bit ADC converts the processed signal into a digital output signal. A feedback path, leading from the multi-bit ADC to the summer, includes at least one dynamic element matching algorithm logic block connected to a multi-bit DAC having a plurality of unit elements. The feedback path minimizes mismatch error associated with the plurality of unit elements. The dynamic element matching algorithm logic block alternately generates an incremental shift signal and a random shift signal at a predetermined time interval for shifting the digital feedback signal by a random amount depending upon the amplitude and frequency of the analog input signal to provide a randomized rotated output to the DAC.
The first embodiment of the dynamic element matching algorithm logic block may include a random number generator connected to a first multiplexer input to provide a random number. A latch receives the digital feedback signal and provides this latched signal to an encoder. A signal dependent counter couples to receive the system clock and the digital feedback signal. If the digital feedback signal is within a predetermined range, a control signal will be generated at a predetermined interval to control the multiplexer. When the control signal is generated at this predetermined interval, the multiplexer provides the random number at its output. At all other cycles, the multiplexer provides the encoded signal at its output. A summer connects between the multiplexer and a decoder to receive this multiplexed output. A feedback delay loop connects from the summer output to the summer input to add a predetermined delay value to the multiplexed output. The decoded signal serves as a shift signal to be applied to a barrel shifter. The barrel shifter includes shifting units that form a shifting column. The first input of the shifting units couples to receive a single bit of the digital feedback signal. The second input of the shifting units connects to the first input of another one of the shifting units. A select line connects to the decoder to apply the shift signal to the shifting units effectuating a shift of the digital feedback signal received by the first input to produce a randomized rotated output.
In the alternative, the random shift signal used to produce a randomized rotated output may depend from a probability variable supplied by a storage unit. As such, a second embodiment of the dynamic element matching algorithm logic block may include a random number generator connected to a first multiplexer input. A latch receives the digital feedback signal and provides this latched signal to an encoder. A storage device having a table of probability variables, clocked by the system clock, provides an input to a comparator. The random number generator provides a first random number to the comparator. The comparator compares the first random number with the probability variable provided by the storage device. The random number generator provides a second random number to the multiplexer. If the first random number is less than the probability variable, then a control pulse is provided to the multiplexer such that a second random number generated by the random number generator appears at the multiplexer output. If the first random number is greater than or equal to the probability variable, then a control pulse is provided to the multiplexer such that the encoded signal appears at the multiplexer output. A summer connects between the multiplexer and a decoder to receive this multiplexed output. A feedback delay loop connects from the summer output to the summer input to add a predetermined delay value to the multiplexed output. The decoded signal serves as a shift signal to be applied to a barrel shifter. The barrel shifter includes shifting units that form a shifting column. The first input of the shifting units couples to receive a single bit of the digital feedback signal. The second input of the shifting units connects to the first input of another one of the shifting units. A select line connects to the decoder to apply the shift signal to the shifting units effectuating a shift of the digital feedback signal received by the first input to produce a randomized rotated output.
Advantages of this design include but are not limited to an SDM having the innovative dynamic element matching algorithm logic block that gives a first order noise shaping of the errors associated with the multi bit DAC employing unit elements, without creating large in-band tones. The dynamic element matching algorithm logic block disclosed achieves drastic reduction of in-band tones in DWA while maintaining SNRD at higher signal amplitudes.
Although the first embodiment and second embodiments are described in the context of a DAC, the teachings of the present invention may also be applied to ADC""s and any other application where dynamic element matching is deemed necessary.